Hello, I’m still working on my PCB, and I’ve made a ton of progress thanks to all the videos and advice I’ve received. I’m nearing the end of this first design iteration, and I’ve run into a tricky situation and I’m looking for tips and advice:
I have a “U”-shaped PCB. On the one side is my 3V3 power supply, and on the other side is my MCU with integrated ADC. spaced along the outer edge of the “U” are 4 externally connected ports, which have 2A max current & 8MHz max SPI buses. I’ve set up instrumentation amplifiers (with a built-in comparator) on the high side of the power to these connectors in order to monitor power consumption with the MCU’s ADC & trigger a fail-safe shutdown with the open-collector comparator outputs.
Due to the shape of the PCB, the component density, and the cost difference between 4 and 6 layer boards, I need to route the SPI, low-speed GPIO/failsafe, the INA output, and a PWM trace roughly parallel to one another. Due to the power needs of the design, the stackup I’m using is:
Top: components, high power rails
Inner 1: low power rails, extra signals that don’t fit on Inner 2
Inner 2: most signals
Bottom: ground plane
I’m looking for tips and advice for how to approach routing this mixed-signal design, given that I don’t think I can follow general best practices (since the analog and digital portions need to be clustered around the external connectors), and I don’t have space (or the design to increase cost) by adding I2C ADCs to locate near the amplifiers.
Here are some ideas I had that I don’t know about: When I need to use multiple layer changes to route through a tricky, tight area, should I prioritize the analog or the high-speed digital traces? Should I make “shields” around the analog traces by running them on Inner 2 and adding a narrow ground shield on Inner 1? Would I need to via stitch such a shield (I don’t have space to via stitch)? Since my ADC sampling rate will be every ~20-30ms and I’ve got a lowpass RC filter on the INA, does this even matter? Should I make the analog or digital traces thicker (I’m using 5mil traces for both)? Should I change my layer stackup in some way?
I’ve been operating under the following routing “algorithm”: first, I route the very high power traces, because thermal issues give me major constraints. Next, I route the high speed signals (UART, SPI, I2C) on inner layers as straight as possible, avoiding crossing under switching power supply current loops. Next, I route functional modules, like the INAs and other ICs. Finally, I route the low speed signals and analog traces wherever they fit. I figure the low speed/GPIO traces can meander tons without any issue, and although I managed to get the analog traces to be roughly straight-shots, 2 of the 4 analog traces have 4 layer changes (where ideally there would just be 2 layer changes to route on an inner layer).
I know this is a lot to write, but my research is coming up short, since everything out there focuses on separation, which is a non-starter on this board due to the density, space, and geometry constraints. Thank you for your advice!