Hi!
I’m designing a 40 ports Solid state relay switch and I need to monitor each port for voltage and current at about 1Ms/S. I would also like to store the streaming data in an SDRAM (3.3V compatible) for the last 8 seconds. So using a 128Mbit should do.
My initial idea is to use two 30-50 cent microcontrollers, one for current and one for voltage (one to high side and one to low side of the SSR driver) and then let them output 8bit each to the the memory pins and then have a third IC to control the Memory addressing. All this three would run in sync using some common clock source.
To add on this I will stack this boards. To about 8 boards in total and could probably have around 16 of this stacks in one system.
So this would leave me with about 120 microcontrollers and that would give me three challenges:
Which bus should I use? I could decide to only communicate with the Memmory chip that would reduce it to 40.
Since I will run sensitive analog signals through this board will I have problems or will it be solvable with a multi layer board?
How do I program them? Is JTAG dasychain the only option other that some switching needle bed?
When I work on (the hardware of) Distributed Control Systems, we used the normal method of passing data between different nodes (RS485) to also pass firmware packages. The package handling was done from a master node to individual subordinate nodes. This required more memory and processing to allow the node to receive and store the package and then boot into that new program. This would require that the micros show up preprogrammed with a bootloader, I believe. That would allow your first program to get down the bus to each node.
Not sure if it’s a great method for what you’re trying, but thought I’d share how I’ve seen it done on large systems in the past.
When thinking of aggregating 1Ms/S times 8 bits times this many channels, your getting into Gb/s range. 10.24GBps actually for Voltage and current on 40 x 8 x 16. 640Mbps if each stack is stand alone.
Does the full data rate need to be sent on the bus or just control and alarm signals?
I think that you are right on that ising a MCU is probably the cheapest Logic plus ADC solution that you’ll find. It would be nice if you could do everything lowside or have isolation built into your highside current sense with a hall effect current sensor or a current transformation. Otherwise Level shifting gets expensive.
Like Chris mentioned, some kind of multidrop bus like RS485, CAN, LVDS could be convenient for routing however you will be hard pressed to get more than 500Mbps out of a bus like that. Even 500 would be tedious. 1Mbps, no problem. Remember too, you can use CAN physical layer without the CAN protocol/controller if you want.
If it really needs to be synchronous, then some kind of shift register is in order. Probably use a small fpga to aggregate all of the streams into one, you can them probably attach one SRAM to this FPGA and save distribution of a bunch of them.
BTW, there are some cheap micros with shockingly high sample rate ADCs. ST has some, I think ATSAML10 is another good example. This family of parts also have some very flexible dmas and event triggers that you can use to make it behave very FPGA like.
60V is the target but it might be -30V to 30V or -12V to +48V. The current is not set yet. I have plans for maybe using an optoIsolated gate driver but initially I have been looking at about 1A or 4A but it would be neat to lift the capability to say 20A with a gate driver and two mosfets but I guess it some catch…? This will be a generic product that I will use for all my clients. No It’s normal SSRs since most of the time it’s DC I switch.
I think more details are needed to appropriately constrain the problem.
I was initially skeptical of using individual uCs as as ADCs. but then I remembered a Cypress evangelist once telling me, years ago, that one of their processors, which sold in huge volumes, were less expensive instrumentation ADCs than non-uC instrumentation ADCs with comparable specs.
What’s driving the need to have a separate ADC measuremtn at the low and high sides? Current is current, so unless there’s a requirement that you hadn’t mentioned, it seems like you might as well measure that at the high side as well. You can then halve the interfacing between the “ADC” and whatever downstream processing you would need.
Then feed that into a really fast I/O heavy processor with memory. Trying to feed SDRAM from multiple masters seems like more trouble than it is worth.
Isolated gate drivers sounds like a Good Idea if 4-20A is being switched. There’s pretty much no reason ever to not use a multi-layer board these days, but a multilayer board in itself does not guarantee you won’t have signal integrity, noise, or EMI issues; you will have to pay close attention to current paths.
Great thought and if this is implemented in the STM as @LukeBeno pointed out I could maybe use JTAG and dasy chain them. But It sound mor stable using RS485 or standard UART…
I must say I’m most great full for all response this have propelled my thoughts so much further.
@LukeBeno as you both has pointed to there is much I have left out. So I will explain some more. There is no need to stream the data all data just need to be stored for the last 8 seconds (would work with less but 2-8 would be nice). Then when the system is stopped due to external instruction or internally the system can fetch data from each individual RAM when i’ts needed to inspect what did happen and be able to scroll through. So the buss speed will need to be about 500kbit/s. So the buss will not need to be to fast.
My constraint is:
*Space is a constraint since I would like to fit the complete system in a box which is about 550x450x200mm.
*Signal integrity is of great importance since one the signal switched are measured by other systems.
*Robustness of the system and downstream systems. So the dynamic watch of the current and voltage is to
ensure no damage to the SSR and the connected systems.
*Logging of as much data as possible to ensure no need for rerun to understand why things happened.
Budget…as always that is a factor.
This is not how I ment as I thought I would use two ICs to drive a driver I would use driver side low and high. So that if both ICs (current and voltage) would agree that all is fine the relay remains open but as soon as one decide that is not ok that IC just switch the pin and the SSR closes.
Great I think that would shave of about 50% of the SSR cost, but that would increase the space need. So many tough decisions.
That one seems perfect. I will look in to using an F3 or F4. 4 ADC at 5Msps is crazy. And The cost would be about 40% lower per Msps but the logistics of using only one Memory would be nice. The only problem I see with that solution is that the largest 3.3V compatible RAM I have seen is only 512Mbit. The higher ones is lower voltage… I could use two and do multidrop on the dress pins and feed two memorychips.
Oh, hmmm, a bunch of MCU’s now have comparators as well as ADC’s, so that you could probably implement high and low-side checks within the same MCU and have it inhibit the channel as soon as a comparactor tripped.
STM32G4 also seems like a more modern alternative to F3. Also probably has multiple IO power domains to interface to lower voltage memories as well as 3.3V analog.
Isn’t an SSR already isolated from the contacts?
Seems like you can keep everything lowside referenced with the proper current sense circuit.
That would improve the protection level even more. That though did give me one more thing to solve. How fast is fast enough for a protection circuit. The HAL sensor for current is 1Mhz so that is why I aimed for 1Msps since the low cost MCUs seem to be in the same region for the ADC ample speed.
This depends entirely on how easily your load(s) will release their magic smoke. Some loads can withstand substantial overcurrent with only a bit of heating; others will vaporize in microseconds. Without knowing what you’re monitoring/controlling, it’s difficult to comment.
I don’t know what I will be monitoring since this will be a generic product which will be used for all kind of systems. So it could be ADCs, FPGAs, resistors, caps, Opamps and so on. So that question is more of a what is good in general. Normally my gut feeling is like 1 ms, but that is just based on some data sheets I have read in the past not any solid industry standard… But I totally understand your point! Don’t get me wrong.
Well, on processors that I know of, the comparator would fire off an interrupt, so the response time would almost always be faster than reading the ADC result and acting on it. You just have to ensure that you are not masking the interrupt with a long running ISR.
Some devices have comparator output pins which you could use to drive a latch that shuts down the relay with hardware so that it would be instantaneous. You might need to filter the response, actually, so that you can tolerate glitches.
If it was only DC, I’d suggest looking into some “SmartFET” type products as an alternative to SSRs. They’re available in high-voltage and high-current models, include overcurrent and thermal protection, are logic-level controlled, and often have current monitoring outputs (albeit not usually very accurate).
