Oh that is a nice part that I have not heard about. Seams like a good pick when dealing with only DC. Sadly that is not my benefit since I don’t know now what type of signal will go where or rather I don’t want to think about what signal goes where. But for driving solenoids and similar loads that would be great. Thank you for all feedback!
I’d like to pop in for just a sec and hopefully avoid you some future headaches - if you’re actually intending on using S D RAM, you should note that DRAM variants require very different controllers than simpler SRAM types. Don’t expect to be able to just spit data onto its DQ pins and run the address lines naively. You’ll need a controller of sorts, and that controller will probably have to have some buffering/caching if you intend to have a rolling buffer (DRAMs require periodic refreshes, during which they can’t be used). Sounds like a fun and challenging project!
Do you have your favorites? I’m currently in the market for using smaller smart FET’s (< 1 amp)
The only one I’ve ever designed into anything is this 70A bad boy:
It’s proven to be pretty darned bulletproof.
Oh that is great info! Saved me a month or two of headache. I will now go down the road of a single STM32F3 chip with 4 ADC at 5Msps and use scan mode to cover 8 SSRs (2 ADC measurements, current and voltage per SSR).
Hrm, not sure? What was the context or the timestamp?
This weeks episode at about 1:04:00 … or maybe it was a different discussion about relatively the same topic
Oh yeah! That was here I think. Jeez, my brain is turned off these days.