I’m sure it’s interesting content. I’m also sure the way it’s written could lull each of us to sleep each night 
I’m usually somewhere between, “OH CRAP I FORGOT ANY AND ALL TEST POINTS” (my younger days) and putting critical test points out to the edges in cleared away areas that a flying probe machine could get at. I have never considered doing all nodes, simply because it is not practical on space constrained designs.
I would say it’s a smart idea if you have any inner layer captive traces that are only coming to the surface at vias. You could also untent those vias for probing, but that is much tougher.
Another consideration is the fact that having any and all of these tests points exposed means there is the potential for shorting, though you could always seal the board after test (using conformal coat or similar)
I would think about this document like the soldering documents for the aerospace industry: A best case scenario for a high risk design…and you can choose how much to follow it or not. I know @dan_h has taken some IPC classes recently, he might be able to speak more about the actual application of this standard and how it will impact design outcomes.