Test points and IPC-SM-782A

I’ve been reading IPC-SM-782A Surface Mount Design and Land Pattern Standard. (Don’t judge me. I thought it might be interesting, and it does indeed have some interesting things in it, despite the resolute attempt by the authors to make the material as dry and boring as possible.)

One thing they talk about is test points. Their recommendation seems to be that you bring every single node of your circuit out to a test point, with the test points laid out on a 1.25 mm grid, presumably to make probing easier. I say “seems to be” because the standard is written in standardese, and I am not a native speaker…

Does anyone do this in real life? I can see the benefit, and I can see the point of having a policy to do this written out up-front, so that you know you need to plan for all those test points, but I’ve not yet seen any designs that actually follow this policy.

I’m sure it’s interesting content. I’m also sure the way it’s written could lull each of us to sleep each night :smiley:

I’m usually somewhere between, “OH CRAP I FORGOT ANY AND ALL TEST POINTS” (my younger days) and putting critical test points out to the edges in cleared away areas that a flying probe machine could get at. I have never considered doing all nodes, simply because it is not practical on space constrained designs.

I would say it’s a smart idea if you have any inner layer captive traces that are only coming to the surface at vias. You could also untent those vias for probing, but that is much tougher.

Another consideration is the fact that having any and all of these tests points exposed means there is the potential for shorting, though you could always seal the board after test (using conformal coat or similar)

I would think about this document like the soldering documents for the aerospace industry: A best case scenario for a high risk design…and you can choose how much to follow it or not. I know @dan_h has taken some IPC classes recently, he might be able to speak more about the actual application of this standard and how it will impact design outcomes.

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I do know that probing on vias is not recommended as it could damage the vias.

Usually, I put test points where I think I might need them. This is based on experience and thinking in detail about bring the board up and what might change in development. Many times, test points are removed to make reverse engineering the board harder on production releases.

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We use a grid. The main reason is that if you introduce a PCB change, you can easily add a new nail in the test equipment and avoid respinning the bed of nails fixture (which is very costly)

There is no added risk of shorting since you have exposed leads on all the components anyway

That said, we try to do as much testing using the microcontroller on the board to remove test points, but the rationale here is that a test point takes up as much space as a small SMD component

Does this mean you’ll leave some of them unpopulated for later?

Maybe there needs to be an online service that reads out standards documents to sooth teething babies.

That was the thing that really made me think about whether this was practical. The smallest footprints for resistors and capacitors covered in the version of this standard I have are 0402. If that’s the smallest thing you have to worry about, having test points for everything on a 1.25 mm grid doesn’t sound too bad. If you’ve got 01005s, BGAs, 10+ layer boards, it doesn’t sound so practical. I now see that the version of the standard I have is dated August 1993, so it may only be of historical interest.

That makes a lot of sense.

Yes, the bed of nails is drilled in a grid. So easy to add a nail

Sorry, don’t yet know how to add comments in line of your comments

Ouch. This is a funny thing. Coming from the software industry, reverse engineering is really much less of a concern. I worked for one company that acquired another that had a realtime spreadshseet product (this was a long time ago, pre-Google, more or less pre-internet even) that we needed to take on and support. Honestly, even having the full source code to the thing, it felt like it would have been easier just to rewrite it from scratch sometimes than to figure out what the original authors were trying to do. But in electronics, this sort of IP protection really seems like a big deal. I recently did some work for someone whose background was in semiconductor processing, and he was absolutely obsessed with IP protection, to an extent that was hugely detrimental to his small company.

For some things, I can understand the worry. But most of the time, it seems as though the really genuine and new IP content of anything (whether it’s software or hardware) is relatively small.

In your case, is the reasoning that you’ll never want to do field repairs of a unit, so the downside of removing test points once you go into production is basically zero?

If you use flying probe instead of bed of nails you can probe on a thin trace where the solder mask is removed

The application was consumer IOT devices. They have over the air software upgrade, but they are not repairable.

For testing an unpopulated board, I leave it up to the board house to work with (usually flying lead).

For populated boards that need functional testing. I normally start with all useful nets on testpoints in the schematic. This means actual signals that matter for testing and is usually just about everything the micro is inputting and outputting. I don’t put points inbetween resistors and LEDS or in the middle of filters. If the end result of the trace is not behaving correctly you don’t care what else is happening. And if you want to save the board you can probe around wherever with equipment.

I then remove testpoints based on level of importance as I become space constrained. I usually even try to have a couple of spare IO testpoints just for toggling in code during development if needed.

One trick that I learned at a previous job is they would machine a block with the holes for the test probes in it. This would keep the test probes in the exact spot they should be. You then need to worry less about keeping the pins 100 mils apart. Then we would insert mechanical pins to align and lock the edges of the board. The pins would be inserted into this block and soldered directly to a PCB below. Not as nice as being able to add pins on a grid, but it worked really well. We moved to 3D printing the pin alignment blocks instead of machining them which saved a lot of money.


Nice document!

Every high volume application I’ve worked on has had this as a hard requirement. The manufacturing organization (in-house and out-house :wink: have demanded it. Since most of what I do is RF, it’s presented challenges in some cases. Not too many. Normally I can absorb the capacitance into a matching network or filter.

I’ve only had one case win an exception - when I demonstrated that the cost of accommodating the test point exceeded the value of the test. The tiny capacitance of the test point isn’t so tiny an impedance effect at 10 GHz. I had to add a lot of parts to overcome the effect of the test point and add a lot more test points.


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Test points for your test points? I’m imagining some sort of Escher-like infinite regress of test points now.

(I also like “out-house” manufacturing!)

Actually test points for the additional circuitry required to accommodate the required test point pad and still meet performance requirements.

There are a lot of CMs I like, but some are definitely in the out-house category.