I have created a schematic, see the attached screenshot. Now I am trying to simulate how it works in a digital SPICE simulator (built-in DipTrace 5.0 beta).
In general, it works almost reasonably. But there are strange signal distortions on some outputs of U3 on each falling edge of the clock coming to the input of decade counter U5. I have shown the problem with red marks.
What I am doing wrong? Is it a simulator issue or the schematic is incorrect?
You are using an asynchronous counter, this means the outputs of the count are not synchromized and do not all change at the same time and there will be propagation delays from each stage of the counter outputs. What you are seeing is the effect of those propagation delays.
Thank you for your help. Bests regards.
Asynchronous counters certainly have their applications, so it’s really up to you to determine whether these glitches are likely to cause a problem. Because asynchronous counter outputs are prone to such glitches, they are best avoided unless the glitches won’t cause unintended actions. If the glitches are likely to cause problems, you can switch to synchronous counters or use latches (or other synchronizing circuits).
