I was doing some reading trying to get a better handle on pull-up resistors and I found the spark-fun description to be very handy. It does leave me with a question, though. In this very common construction from the spark-fun article:
I understand the reasoning for the resistor. Since it is (supposedly) 1/10th the impedance of the pin it is connected to; is there any reason I can’t put the resistor on the opposite side of the switch? Is the placement for anything other than guaranteeing the button route is lower impedance? Wouldn’t placing an appropriately sized resistor on the other side of the button reduce the extra impedance being placed on the pin?
Thanks for taking the time to answer my very elementary questions.
Hi Tim, I’m not sure quite what the aim is but if the resistor tied to VCC was connected to the left side of the button/switch, the mcu input would not be influenced by any of potentials on the left when the button is open. This means that if there’s no internal pullup or pulldown resistor set on the mcu input, it would be at a “floating” potential, likely meander across the range 0-VCC. If you read the pin input while floating, it could give you logic high or logic low results (even though the button is open), which renders it an unreliable way to tell whether the button is actually open or closed.
Please say if I have completely missed the point of your query and I’ll try again.
Also, there would be a constant current on the LHS, which increases power requirements unnecessarily.
The whole purpose of most pull-up (or pull-down) resistors is to keep inputs at valid logic level voltages in the absence of an input signal. The resistance value has to be high enough so that the input signal isn’t distorted too much. But because FET inputs are extremely high resistance any stray currents (leakage from the pin or the source, or radio-frequency energy coupled onto the pin) can cause the pin voltage to fluctuate wildly, causing the input to flip back and forth. The pull-up/down resistance therefore has an upper limit as well.
Because electrical engineering is hard enough already, we like to use rules of thumb to guesstimate reasonable values. And because factors of ten usually keep stray voltages low enough, we love to use them. In this example the pull-up/down resistance is usually no greater than 1/10 of the input pin impedance and no less than 10 times that of the source (driving circuit) output impedance.
As far as location, we always want the input pin to be connected to a valid logic level, so we almost always attach the pull-up/down resistor directly between the pin and a voltage rail (whichever rail keeps the circuit operating properly when the input signal source isn’t connected).
Maybe I am making an bad assumption that there is already resistance within the mcu, just because there is impedance within the mcu. I do realize that the resistor is required on the button path to stop undo loss of power when the circuit is closed. I was just wondering if being able to detach the value of the resistor from the pin itself would allow for a larger resistor to further restrict use of power and to keep from having multiple resistances in the mcu path.
The answers here seem to indicate there is not enough resistance in the mcu pin path for the level to be something other than floating. … or have a missed something in my understanding?
The input is really just a FET gate. So floating input.
The pull up is used, since the switch is coupled to GND. Otherwise the input voltage level to the IO is not defined
Ahh, I see where I misunderstood. So on an FPGA pin, there may or may not be a resistor already present depending on the chip and configuration; but this is by design for this very reason not because the internal structure automatically provides resistance.
As always, thanks for the explanation everyone!
Yes, I think you understand now. Unless the datasheet states that FET inputs have pull-ups or pull-downs, it’s best to assume that you have to provide them.