MOSFET with higher thermal resistance has higher power dissipation?!

Here are links for the 2 MOSFETs for comparison. I cannot understand how the MOSFET with higher thermal resistance is able to dissipate 20% more power than the one without. Anyone have an idea about this?


Addendum: Ok, I’m not allowed to include links… argh. Here are the part numbers:

The IXFK180N15P data sheet says 830W and max 0.18C/W Rthj-c.
The IXFH94N30P3 data sheet says 1040W and max 0.12C/W Rthj-c.

What makes you think “the MOSFET with higher thermal resistance is able to dissipate 20% more power than the one without”?

I was looking at both the Rth-JC and the Rth-CS values. 0.25C/W for the 1040W IXFH94N30P3 and 0.15C/W for the 830W IXFK180N15P.
From what I understood, and forgive me if I’m wrong, you have to add both values in your calculation for thermal impedance. Resistance Junction to Case and Resistance Case to (heat)Sink.

The power dissipation spec is given with the assumption that the case is being held at 25C. I think this removes the case to sink parameter from the equation.

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There is no direct correlation between thermal resistances and maximum device power unless you assume the same heatsink thermal resistance.

The (very) simplified thermal equation is

Tj = Tamb + Pd*[Rθ(jc) + Rθ(cs) + Rθ(sa)] ,

so to determine the maximum heatsink thermal resistance you solve the equation for Rθ(sa) using known values for the variables - where Tj = Tj(max):

Rθ(sa) = [Tj(max) - Tamb]/Pd -
Rθ(jc) - Rθ(cs)

The device thermal resistance values Rθ(jc) and Rθ(cs) are given with Tj=25°C, which for most applications will require some sort of active cooling or other refrigeration.

There is no direct correlation between thermal resistances and maximum device power unless you assume the same heatsink thermal resistance.

Power dissipated in the MOSFET needs to be drawn away from it fast enough to avoid thermal overload.
To that end, I was asking how to better understand how one MOSFET, given an increased thermal resistance, could handle a higher power load (W).
I am aware of the formula you just gave, but thanks for reposting it anyway, it can be hard to relocate it on the net. (I really should memorize it…)

In the two examples given, in addition to the IXFH94N30P3 having higher thermal resistance than the IXFK180N15P. It has a higher RDS on value of 36mohms. The IXFK180N15P has a lower RDS on resistance of 11mohms. This translates to a higher thermal gain when loaded.

I’m not trying to be dense or something. I have no clue.

The lower the RdsOn, the lower the power dissipation of the MOSFET (W = V x I = (R x I) x I = R × I^2). I.e. a MOSFET with a lower RdsOn can pass more current for the same max die temperature (everything else being equal, and with suitable gate voltage such that the stated RdsOn is actually achieved.

Edit: Sorry, I didn’t take the time to figure out which device was which, and ended up just stating the obvious instead of giving anything useful. Doh!


No problem, and I can understand why my response might have been confusing.

Something that isn’t obvious is that two different manufacturers (or different product groups of a given manufacturer) can define the test methods differently, and the junction-case and case-sink thermal resistances don’t tell the full story about heat transfer. This is especially true when the two devices have different construction, or even the same package but different die sizes, different bond wires, and numerous other seemingly insignificant differences that actually are often extremely important. For example, the amount of heat drawn away by the board through the leads is not accounted for in the simple model usually used (the one I gave in my response), and in many instances this is one of the major heat sinking paths. This is one of the biggest reasons why the simple model has been superseded by a significantly more complex model. I can show the newer model here, if desired.

Ah! That makes sense.

Yes, please do post the newer model.


Operating voltage is 2X so current is 1/2 for the same power level.

Rdson is ~3X, so Die power is ~3/4 at the same power level. Current is square law relative to power, so 1/2 current is 1/4 power, but linear with resistance.

Theta JC is lower for the higher power part, so it can dissipate 1.5 X power for the same Tj assuming all else if the same.

All else is not the same. It never is. These are all datasheet values, so they all assume Tc (not Tj) is 25C. The lower thermal resistance gives the higher power part an advantage. The die stays cooler at the lower thermal resistance. I dare you to find that in a useful design that operates with a package temp of 25C. The power test is also specified at very low duty cycles (less than 2%) to keep the test fixture thermal mass dominant in the measurement.

You could chalk this up to specsmanship and lying vendors. I’m sure there is some element of that at play, but the fact is that the vendor can’t predict your application, so they control the parameters to normalize the data. I know it’s shocking that they do so in a manner that puts their parts in the best light. :astonished:


Rather than actually post it - and have to explain the rationale behind it - here’s how Texas Instruments addresses the issue. [Warning: Anyone not involved in thermal engineering may be more confused after reading it, but after a few (dozen?) more times it should make some sense :)]

How to Evaluate Junction Temperature Properly with Thermal Metrics (Rev. B)

Another (IMHO more readable) treatment of the subject can be found here:

Use of JEDEC Thermal Metrics in Calculating Chip Temperatures (without Attached Heat Sinks) (

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Thank you everyone for your replies.
Although I may have to ask (by opening another thread), to better understand the fine materials that were linked, I consider this question to be solved.