I recently had a PCB fabricated and the CAD technician that reviewed the Gerbers reported “Various solder mask openings were trimmed to allow for 2mil clearance to nearby copper”. The design was made with KiCad v5.1.4 on 64-bit Windows 10.
Most of the footprints came from the standard library except for the QFN footprint (which I created using the QFN wizard), and the reverse-mounting LED footprint (which I modified from a footprint in the standard library). However not all footprints failed. Now after testing I need to revise the board, and I’d like to avoid the two-hundred mask-to-copper violations again.
Is there a way to easily correct this? I feel uneasy when a vendor modifies a a design to this extent. Could the pour parameters be incorrect?
For context, the board is a two layer, approx 4" round, and has 119 placements of 53 unique MPNs (mostly 0603 passives, 30 reverse-mounting LEDs, a TQFP MPU, a QFN LED driver…).
The CAD tech elaborated “the solder mask shape present in the files did not match that of the copper pad and pour. This is acceptable in most cases however, we require a 2 mil clearance from nearby copper (in this case the ground plane) to guarantee the mask will prevent bridging during soldering.”
Screenshot from the CAD tech reporting issue:
Screenshot showing my comparison of my submitted mask file to the “fixed” version from the CAD tech.
Mask constraints I received from the vendor afterwards (not included in their standard "PCB Capabilities chart).
Curiously, the constraint violation was reported by the domestic Canadian fabricator I am using for production, while PCBWay in China previously fabricated five prototype boards and did not report violations (although I wonder if they silently fixed the same issues reported by the domestic fab).
(I have also posted this to the KiCad forum)
Thanks for your help,
Dale
