Low end CPLD/FPGA for switching interlock design

Thanks for all the ideas – learning about a many parts that I did not know about.

What are your reasons for this? Some of these parts seem well stocked at Digikey, but maybe that won’t last.

This is what has been done in the past, but we want the ability to change the timing (be reprogramming the logic device in system) if needed. The discrete component approach fixes the timing and requires rework if anything needs to change.

That is an option, but we would really like to have two devices involved so there is little chance of failure if one device fails. There are relays and other high power devices switching close by, so potential for noise. We could use two MCUs …

Very interesting!

Seems like a very good fit as we could no doubt leverage the mixed signal functionality.