We are working on an interlock circuit where we’d like to use a FPGA/CPLD in combination with a MCU to in a switching circuit. The basic requirement is that both switches can’t be on at the same time, so the FPGA will enforce the timing such that switch X has to be off for z amount of time before switch Y can be turned on. Basically the MCU and FPGA would have to agree before a switch could be turned on to reduce the possibility that both switches could be turned on at the same time.
Some things that seem nice to have:
- instant on would be nice, but not sure if absolutely required
- enough logic to implement a few counters and some simple logic
- be re-programmable in-system so we can change the operation if needed
Years ago, we used Xilnix CPLDs in applications like this. Still seems like it might be a reasonable option as they have 3.3V power (better noise immunity), etc.
Does anyone have any suggestions? I’ve been out of the FPGA design space for quite a few years, so likely not current on what is available.