Noticed something ‘interesting’ in the LM1084 datasheet (this is a 5V 5A linear regulator). The datasheet mentions that it can be used as a “Post Regulator for Switching DC-DC Converter”. I’m wondering what applications would need both a switching regulator, and then an additional linear regulator? Any ideas? Would having two regulators cause a lot of noise on the circuit? Thanks!
Here’s the Digikey part num: LM1084IT-5.0/NOPB-ND
That’s a great question!
I have used linear regulators after a switching regulator before in order to take advantage of the Power Supply Rejection Ratio (PSRR) of the linear regulators. This means it will help to effectively filter out noise due to the switching regulator.
The LM1084 has this listed as “Ripple Rejection” and spec’d at 75 dB at 120 Hz:
Really you need to look at the table to see the rejection ratio over the frequency range:
Most linear regulators are just tiny control systems, so the system has a natural “roll off” that corresponds to the frequency response of that control system. Small spikes that are not supposed to be there will be squashed by the control system.
As with any linear regulator, you’ll need to have some amount of voltage differential between in and out, so that’s important to know for designing your system. So maybe you use a switcher to go from 24V down to 7V (if it’s adjustable) where you can efficiently convert down to a lower voltage, but then you put the 7V into a 5V regulator to help “clean up” the signal; the cost of doing so is that final 2V you drop in the linear regulator, at say, 1A, would result in 2W burned on the linear regulator.
This is all less important if the 5V is going into something that will introduce more noise (digital, motors, etc). But quite important in analog!
@ChrisGammell’s answer nails it.
TI also has this great app note showing how linear regulators are great for noise management. It also hints at some of their imperfections - particularly how the LDO voltage reference is typically the constraint on overall noise referred by the LDO.
https://www.ti.com/lit/an/slyt201/slyt201.pdf
I’ve seen some clever methods for dealing with noise like this, and keeping it out of ADC/DAC voltage references - particularly capacitance multipliers, and dual-bootstrapped RC filters for reference sources. (I’ll send a SCH snippet of the second when I get to a place I can doodle one.)
While a linear reg, if chosen correctly and especially if designed specifically for this type of application can result in less noise than is present at the SMPS’s output, it’s not a given, as pointed out by our own @TomAnderson in his most excellent app note: https://www.tempoautomation.com/toms-circuits/power-supply-filter-design-for-pcb/
At the typical SMPS switching frequency of several 100 kHz the ripple rejection advantage won’t be all that great. Capacitance multipliers are good alternatives
A post regulator can be used to ease the requirements of the SMPS. Load transients will be damped by the linear and you can use lower output caps of the SMPS (if loop regulation is still satisfied)
To back up @ChrisGammell, JuliaTruchsess and @kvk the cheap TPS7A24’s ripple rejection (Figure 15) is not even characterized above 10M in the datasheet, and at 100K its about 20dB, rising to 30dB at 1M. (The older LM317 is actually much better than this, starting at 40dB!). A much more expensive unit LP38798 can do 50dB out to several MHz (Figure 2).
“If you ask a (digital) signal integrity engineer how many harmonics you care about they plead the 5th!” (old joke), but a squarish switching frequency of 100K will have maybe 1/3 of the energy of the 100K fundamental at the 300K and 500K harmonics, which is pretty significant, with energies staying high the harder the switch is.
I’ve never heard this but as an SI dilettante I love it. 
SMPS followed by linear regulator is a standard toolkit item to step down voltage to a clean output that is ready for analog power. The linear supply provides superb PSRR as Chris Gammell pointed out.
I would additionally suggest that you use ferrites on the input to the SMPS (to protect the noise on the input), followed by ferrites on the output of the SMPS (after the fb node), as well as ferrites after the linear regulator (after any fb nodes). The ferrites will get rid of the switching noise that the linear can’t touch (and the caps can’t touch either).
A great explanation of this comes from Linear Technologies Jim Williams App note 101. Jim was a great guy - met him once. His breadth of knowledge was pretty amazing. Here’s a link to the app note. They don’t teach this stuff in school, unfortunately.
Mike
Go figure there’s a Williams app note for this!
He seems like he was a fine person. Smart, hard working, always learning.
I love the test circuit he builds in the note!
I recently stumbled across this at work - I was updating an old board, when I noticed a LDO following a switcher. I recalled Dave Jones’ (https://youtu.be/wopmEyZKnYo?t=329) video on LDO’s having a poor PSRR at higher frequencies, so decided to test it out experimentally.
Ignore the frequencies below 1Khz, I was using a common mode choke as my injection transformer and it had poor performance at lower frequencies (as you’d expect). This was a 7805, an older IC I think, and it has pretty poor attenuation at the switching frequency (100KHz).
However, a newer model (this time thought it was a 7812, I didn’t have a newer 7805 to hand) has much better performance, and has around 65dB of attenuation still. This was the LDO they were actually using, so I left it in the design as it should attenuate the switching ripple significantly.
Just thought I’d show some experimental results for the discussion, as I was under the illusion that they didn’t attenatue HF ripple.
Could you, if you have this on the bench, do a FFT of the injected noise (assuming square) and also extend your FFTs to look at the 3rd and 5th harmonics at 300 and 500kHz? Its a bit tricky to see how well the LDO is doing without the input values (or I am reading your graphs wrong!) and I am expecting a lot of energy in 3rd and 5th where the LDO is even less effective.
Great to see you on here, Mike! You may not remember me, but I’m Duane Parks’ son. At Praxsym we were in mourning when Williams and then Pease died.
Shannon! Definitely remember you, and so glad to see you doing well. Listened to your amp hour episode and was engaged and interested the whole time. Very cool stuff you’re doing with audio and dsp.
Jim was a unique guy. He came to Cytomation years ago with the LT guys that normally came by. We built flow cytometers, which are pretty niche, but he knew all about them and was able to carry on an intelligent conversation about them. Hope to always stay curious like Jim.
Hey everyone, thanks for all the info and replies! It is useful to know the applications of this. It seems this technique would be useful for going from a 4 cell lipo (14.8V nominal) with a SMPS to 6V for motors, then with a linear to 5V for a microcontroller / sensors. The app notes links are great and will be reading through these as well.
One other thing to keep in mind with linears is that they have to have a minimum input to output voltage to achieve the advertised PSRR. Typically one needs about 2V, even as low as 1.5.
The 1.5V to 2V is for NPN linears. Of you use a MOSFET/PNP low dropout, it’s closer to 100mV dropout.
Example is LM2931
You have to be careful with specs on these. I learned this the hard way. Dropout voltage is the minimum input to output that it can hold the output line voltage. Regulation voltage can be much different. For the 2931 that you referenced, the minimum dropout can be less than 100mV. However, for their line regulation spec, they require at least 0.6V. And for their impressive PSRR graph showing 95dB rejection, they show an input of 14V and an output of 5V.
What does a design need that uses this chip and needs good regulation in the output? I’d say at least 0.6V, but it sounds like regulation could benefit from a little more.
