Yes, the pull-downs on the FET gates are there to turn the FETs off when the uC output pin is not driven, e.g. during reset.
I’m thinking to reduce the sense resistor’s value a bit and put some form of detector on it that turns a high-side switch off, thereby cutting power to all the outputs.
Edit: This load switch with programmable current limit seems to be a reasonable candidate: https://www.vishay.com/docs/65223/sip32430.pdf , need to look around some more…
Edit 2: I ended up going with a TPS1H200A https://www.ti.com/lit/ds/symlink/tps1h200a-q1.pdf, design files for a 10mm x 8mm board sent to OSH Park, we’ll see…