In Need of PCB Stack Up Advice

I’m looking for an 8 layer stack up. No need for impedance control. Here is what I would like to do…

  1. Signal/PWR
    2)GND
    3)Signal
    4)PWR (+5VA)
    5)PWR (-5VA)
    6)Signal
    7)GND
    8)Signal/PWR

My point of hesitation is that both layer 4 and 5 are PWR layers that are next to signal layers 3 and 6. I think this is ok since all the signal layers have an adjacent GND layer… but the two PWR layers 4 and 5 would not be adjacent to any GND layer. It’s not clear to me if this is an issue or not.

Most example 8 layer stack ups I have seen are the same as above except that either layer 4 or layer 5 would be a GND layer so that the PWR layer is adjacent to a GND layer… whereas what I have shown makes layer 4 and 5 both PWR layers with no GND layer adjacent.

Do the PWR layers need an adjacent GND layer? Or am I overthinking this…?

Your signal layers are OK as you’ve noted since they have adjacent image planes.What you’re giving up by not having ground adjacent to power is distributed capacitance to reduce the distribution network’s impedance. How important this is depends on the speeds/frequencies involved.

Often overlooked is the possibility of routing power instead of using planes, which can free up large swaths of area that can be used for ground to add capacitance. Routed power also tends to reduce inter-plane cavity resonances, which can be a major issue.

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Actually, no, on further consideration I take that back. There are going to be fields between the power planes and the ground planes that might wreak havoc on the signals on L3 and L6, as shown in this slide from a Rick Hartley presentation:

In fact, your stackup is given as an example of a bad 8-layer stackup in the same presentation:

I suggest routing +5V and -5V on L4 or L5 and putting a solid ground plane on the other.

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Hi,

That is not a stackup I would recommend. But one we are missing the speed of your rising edges.

Ideally each signal should be referenced to a ground plane as close as possible, being either on a adjacent layer or a coplanar ground pour along the signal. So signals on layer 1 and 8 will do very well. But on layer 3 and 6 the signals might couple with power because instead of ground because that’s the shortest path.

You could also reference your signals to a power plane of the same voltage provided you can add a lot of capacitors from that power plane to ground along the path. But this in my understanding stops working for signals over 100MHz (don’t quote me on the exact number, this is more of a ballpark).

Regards,

Nicolas

Thank you for your help, its much appreciated!

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Do you need the analog +5/-5 plane throughout the whole board?

Without looking at the schematics, I’m taking a guess, but if you have, say, an analog front-end section in your design, I’m guessing that the analog area has much less wiring density than the rest of the system?

Assuming that’s true, I’d consider making L4 and L5 split planes with the analog power only in that analog area, with L3/L6 turned into additional ground references instead of signals.

One possibility I’d like to suggest is to put analog signals on L1 and L3 referenced to a common ground on L2, shifting +5VA and -5VA down. I would put digital interfacing lines to this section on L8.
L1: Sig
L2: Gnd
L3: Sig
L4: Gnd
L5: +5VA
L6: -5VA
L7: Gnd
L8: Sig / Vcc

With this design, you can leave ground continuous on L2 and L7, and connect the digital and analog areas together with traces on L8 and on L1; and then rearrange the use of L3-L6 to give you

L1: Sig
L2: Gnd
L3: Sig
L4: Gnd
L5: VCC
L6: Sig
L7: Gnd
L8: Sig

Make sure you have plenty of vias to stitch things together!

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@kundro85 The original post stackup sounds like bad news for the signals on L3/L6 and/or the planes on L4/L5. E.g. a signal on L3/L6 could couple
as noise onto your L4/L5 planes.

I think @ToyBuilder 's first stackup suggestion is a better plan. L3 could be VCCIO or mixed if you need it. Also, I too have found that because I am usually isolating analog sections anyway, that the split plane or planelet approach can be useful with good performance (but clearances need to be generous to avoid edge coupling of the planes).

Personal habit: Starting the design with planelets can help you plan for keeping the ground current loops separate anyway…even if you are going to use a full layer in the end. Or, you might sometimes find that you can actually drop two layers off the stackup.

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I like that term for this! Stealing it!

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If Charles mentions a personal engineering habit, I usually make it a canon.