Board Layout Question (Robert Ferenec ESP32)


was watching Robert Ferenec’s “How to Make Custom ESP32 Board in 3 Hours | Full Tutorial” and had some questions, I would love other’s opinion on

  1. at 1:24.02 (How to Make Custom ESP32 Board in 3 Hours | Full Tutorial - YouTube) he starts just adding vias to most pads on the ESP32; then at 1:35:00 (How to Make Custom ESP32 Board in 3 Hours | Full Tutorial - YouTube) he starts routing some pins. instead of staying on the top layer, he goes via the bottom layer, then comes back to the top layer… and maybe that makes sense in the long run for later tracks, but is there any other reason to do it this way? I am referring to this track… unless you can’t route a track under the ESP32 on the top layer?


  1. at 1:34:59 (How to Make Custom ESP32 Board in 3 Hours | Full Tutorial - YouTube) i don’t understand why he doesn’t place the via next to the pad, instead of routing so far away only to back track on the bottom layer - is it a clearance issue?

thanks :slight_smile:

1 Like

So, I would first say that you should post the question to his video as well. These sorts of nuances would be appreciated by him and his viewers, and he would (hopefully) respond to your comment.

So it could be that he already has a mental plan in place for how to route them. He may have already done this PCB as a rehearsal before recording the video, so you don’t see the trial and error portion of routing. It could also be that he’s been doing PCB layout enough that he can just see a group of pins and know what routing pattern needs to be used.

Alternatively, there are some conventions or patterns that people use that might explain this. One of these conventions is to designate one layer as a horizontal layer and the opposite layer as a vertical layer. You can see this on the second picture where IO2’s red trace is mostly vertical while its blue trace is mostly horizontal. You end up needing to break this convention near component connections, but if you’re routing a high-density board with lots of IO signals, it’s a handy pattern to use.


yeah, worth a shot; I generally don’t post questions on YT videos as they get lost in the noise!

absolutely, for sure he knew how he was going to route it! I made the same note, “3 Hours” - sure; if you know exactly what you want to do in advance!

ok, so what I’m hearing is, it’s neither good nor bad to do it the way he did it? My concern was I was missing something obvious! but ill ping to the YT video and see what happens

Note: re: question 1 - I see that there are traces already on the top layer, and so he had to go to the bottom layer to avoid crossing the streams traces. What I omitted from my question was that he places the vias to ground on the pads as the first step in routing (so, he knew in advance that those traces had to go on the bottom layer and looking again at it, that is a reasonable bet)

and re: #2 - looking again, this was another case of knowing ahead of time what needed to be done - without placing the via where he did, he wouldn’t have been able to route the traces later… so @seth.kazarians yep, you are spot on; i guess there was some trial and error in the area and we are just seeing the results.

I agree with this. He has definitely done this board before, considering that he knows so many things already: the errata, having to place part of the circuit on the bottom side, etc. If this was his first time laying out the board in real time it would take a lot longer to gather all the info he needs.

As far as where he places vias for partially routing certain signals on the bottom side, I agree that he has his own mental rules. Other PCB designers would likely have different rules, but as long as there are good design rules in place and you remember to run the design rule checker (DRC) it doesn’t make much difference. He knows the fab’s process capabilities, so he knows what to avoid.

that was my immediate reaction as well! 3 hours? Sure if you know what you’re doing … like a TV Chef … “here’s one I prepared earlier!” - but since the video is obviously aimed at beginners, to do that in 3 hours is expecting a bit much; I spent a week on the schematic, then stopped the video to do my own component placement and routing (otherwise I don’t think you will get much learning out of just copy+pasting his solution)

note: I am not having a go at Robert, I like his work and what he does. And sure! if you have everything prepped in advance, if you have the years of experience you can do that board in 3 hours (so, maybe we can say it’s a bar to aspire to?)

I guess this is also where experience comes into play - in Dave Jones layout PDF ( he makes that point as well, that if you give the same schematic to 100 people they will come back with 100 different layouts; That is one of the (mental) hurdles I have to clear am i doing this the right way? or am i doing this the most efficient way and sometimes it needs to be “if i do it this way will i achieve by goals?” (i.e.: will it work)

great point to reinforce setting good design rules and running the DRC; I watched Phil’s Lab (another newish YouTuber in this space) last night route BGA’s and… wow!

but (and this is for my benefit as much as anyone reading later) - the biggest take away is it looks easy watching someone else do it, but try it yourself with no prior knowledge of the solution! (and again, this is the strong benefit of the CE courses, there was lots of “heres the requirement, what would you do” type questions.

1 Like

Short Answer: Yes.

Longer answer: If you pack everything as tightly as possible initially:

  1. You frequently find you’ve “painted yourself into a corner” and have no room to jiggle things to make things fit as the layout progresses.
  2. PCB spacing rules are generally absolute minimums. More room improves yields.
  3. moving the via to the side and down leaves room for more traces parallel to the line of lead holes.
1 Like