Bed of nails protection circuitry

I’m tasked with building a bed of nails fixture for an existing Linux-based product with a wide variety of voltages onboard. DC input comes in at 18V, and we have several step-down/up converters and regulators on the board. I have test points and can add more points as needed, and would like to sample their outputs while executing shell commands on the product over SSH or serial.

I would like to protect the inputs from the board under test. I’ve had at least one case where the 18V input shorted to the 3V3 rail on a current sensing IC. This damaged the board being tested, and would have damaged or destroyed a simple GPIO input on the test fixture.

One idea I’ve had is before applying power, test all of the test points against each power rail and other test points using simple output -> input GPIO logic. This could identify simple shorts before applying power. I’d then need to detach the power rail pins because they will rise to 18V or more. This doesn’t account for other cases where a stray voltage might damage those pins. And adding something like an optocoupler would break the ability to feed inputs into the test points.

Does anyone have any recipes they’ve used with success to deal with such scenarios? What’s typical on a test fixture with mixed voltages?

On the board that has the bed of nails, add a series resistor to all pins
That way shorts will not cause any problems on both the DUT and the test equipment, and your DMM has high internal resistance, so 1kohm in series doesn’t affect the measurement

your DMM has high internal resistance, so 1kohm in series doesn’t affect the measurement

I won’t be testing with a DMM, just a raspberry pi or similar that wants 3V3 max input. 18V through a 1k is still likely to destroy it, correct? I know I can use a resistor divider on those pins. But if I test for shorts using 3.3 volts, that divides down to around 500mV, which is below the on/off threshold of a GPIO, and the pi doesn’t have an ADC.

Once I’ve verified that the voltage rails are not shorted to anything, I can disregard those test points and will only be testing logic level test points.

So you are using the Rpi to test the board?

For bed of nails testing of supply voltages you need analog measurements, or a DAC with comparator.

If you energise the 18V rail with 3.3V then measure the 3.3V rail with a pulldown attached, is that any good?

It is possible to measure analog voltage with a GPIO, but you need a dither signal (PWM with RC) and a reference voltage

energise the 18V rail with 3.3V then measure the 3.3V rail with a pulldown attached

Yes, I have been considering this approach. But I’ll then need switching to detach the 18V rail from the GPIOs before proceeding with the rest of my testing. Seems a little over-engineered, but I don’t see a better way.

Is there much value in using an ADC for every test pin? I suppose an invalid logic value could be a data point for further troubleshooting.

What about a low vf (red) LED and a series diode with a breakdown voltage over 20v between the 3.3V rail and the 18v rail. Then a 1k resistor between 18v and GND. Use an LDR voltage divider set to cover your logic thresholds, heat shrunk or taped to the LED. Measure the LDR voltage divider with your pi GPIO and energise the 3.3V rail. If it is shorted to 18v the LED will be off. If the 18v rail is otherwise pulled down, the LED should turn on.

Edit - optoisolator +diode may allow you to do this but I haven’t checked hence using building blocks of the LED, diode and LDR.

For a production setup, I would add a logger, like this:

Production runs needs to be solid and that is hard with out correct test equipment

An instrument like this costs more, but is versatile and cuts down on development costs

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I’d add a 5-10k series resistor followed by a 3v3 TVS diode to ground. That will clamp anything much over 3v3, including ESD. Has worked wonders for me in the past.

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It is better to use 2 schottky diodes, one to either rail. And a 10k before the diodes and another 10k into the pin (will protect for SCR latchup)

Resistors in series with clamping devices increase the effective clamping voltage by R*I, where I is the available fault current. Fault current can be very high for many nodes - especially power rails.

You can minimize this effect by selecting the lowest resistance that keeps power dissipated in the clamping device so that the maximum allowable die temperature is not exceeded.

Another way to do this is to use a larger resistance and then measure the current. If there is no fault you can engage a relay or other device to short across the resistance for the actual test reading; this is a very common technique used in “smart” bed-of-nails testers.