ASIC fab handoff timing simulation

In all the ASIC chatter recently there has been mention of DRC, but what about corner-case dynamic logic timing with timing models extracted from the layout. NCR required we have empty diff files from corner-case (multiple) simulation runs in the early 90’s for our groundbreaking 0.7um design. It also showed test coverage, which fed their risk. Is this still done? Do the free tools mentioned in your recent podcast episode @ChrisGammell nclude that capability?

I’m thinking a research project is getting incredibly easy, but what about production?