"Active Discharge" LDOs

Today I learned something new that I thought I’d share here. I’ve always taken linear regulators pretty much for granted - you pick one that can handle your current, power, noise, regulation, etc. requirements and after that they’re pretty interchangeable. I’ve seen “active discharge” mentioned on a few data sheets recently but never paid it much attention, assuming it wasn’t relevant to my fairly mundane requirements, but it turns out that it’s a very important feature in some applications, particularly those like my present case, which involves fairly low (≈2mA) baseline current with large (≈160mA), brief (600µs) spikes. I’m using an ON Semi NCP718B LDO, which is inexpensive and has seemingly good specs: you read “10mV load regulation at 300mA” and figure that it’s going to be just fine. I was mightily surprised, therefore, to see 1V p-p ripple on my 3.3V rail whenever my BT radio sends out an advertising packet :astonished:

Big shout-out to ON Semi’s outstanding tech support, who got back to me in a couple of days with this detailed explanation:

"The problem is that the NCP718B has no active discharge. When first current spike appears, regulation loop is trying to open internal power P-MOS as much as possible to cover increased load demand. When current spike disappears, regulation loop needs some time to fully close open P-MOS. During that time, output voltage increases above nominal 3.3V. This is caused by charging output capacitor 10uF through fully open P-MOS and light load condition.

When regulation loop realizes that output voltage is “too high”, it fully close internal P-MOS and output capacitor is discharged by light load only (~1.8mA).

If next current peak appears BEFORE output voltage drops down to nominal 3.3V, internal control loop can’t react fast as internal P-MOS is fully closed. It takes some time to charge gate capacity to be able to control this P-MOS and during this time is output capacitor the only one source of charge for load. This cause that output voltage drops significantly lower than during first transient.

When control loop takes over the situation, output capacitor is charged back by fully open P-MOS and procedure repeats.

In fact, NCP718B Is a bad choice for this type of application. Please use NCP718A instead (A means Active discharge, which helps to return output voltage back to nominal 3.3V much faster after first current spike."

Yellow trace is 12V input rail with 330mV of ripple; blue trace is LDO 3.3V output with 1V(!) of ripple:

Here’s the current drain (yay, Joulescope!):

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That’s really interesting, I, too, always took them for granted. It’s easy to forget that they’re still a little regulator and power stage in there. I wonder if this was common knowledge back in the day when there was no monolithic IC for an LDO, and has since been forgotten.

I also wonder if DC-DCs will end up like this too, with certain things forgotten (specifically on the compensation/control side of things) the more integrated and monolithic they get!

But that’s a great share, thanks!

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A switch mode controls the gate of the switch on/off. So it does not have that problem

The linear has a dialed down regulation loop since the FET is slow, in combination with unconditional stable loop with large output capacitors

Active discharge is bound to have some impact on overall efficiency. It’s almost like engineering is all about solving a set of compromises.

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I took a look at the datasheet since this type of application is very common for Joulescope customers. I find it very suspicious that the NCP718 has no mention of any dynamic performance. I am used to at least seeing a dynamic load response figure.

Here’s one for 100 µA ↔ 100 mA from the MCP1801, another low-cost LDO, but only 150 mA max:

Makes me wonder if the NCP718B has an unusually bad dynamic response. I’d be very interested in what you find if you happen to try different LDOs without active discharge.

Great to see that you are putting your Joulescope to work!

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Constantly! Can’t imagine life without it.

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Hmmm, so it looks like active discharge clamps the output to ground via 100R when EN is inactive…

If you are using this to power your BT module, do you have a separate power rail for the radio? I don’t think I’ve ever toggled an EN signal on an LDO…

Ain’t that the truth! There are no “ideal” components - despite what simulations assume - so real-world engineering is always about compromises.

No, the radio is always on in this design, and the MCU and radio share the same rail. I have some projects where I sleep the radio, but brute-force powering down stuff can lead to unexpected current-drain paths and I try to avoid it.

In that case, I have some doubts as to whether the Active discharge variant will do you any good.

It seems like the solution to the pollution is dilution – in this case, having a much bigger capacitor to cut down on the noise…

It seems to me that it should - the regulator loop doesn’t work with high transients and low baseline current because there’s nothing to pull down the rail other than the baseline current when the pass transistor is off. With active discharge it will pull down the rail forcibly so the loop can recover quickly from the transient. It’s sort of a “pseudo push-pull” output vs open-drain.

But it only pulls when the regulator is disabled, right? But I think you are running with the regulator always ENabled?

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I actually have the same question: I always read the “active discharge” option as:

“Does your application have a lot of bulk capacitance, but you’re trying to quickly POR-reset a circuit by powering off the LDO instead of individually resetting each chip that matters? Try our Active Discharge option, instead of smacking a huge resistor on there to burn power all the time!”

It’s interesting that your app engineer mentions active discharge as relevant to control performance, given that the datasheet itself offers no indication of that whatsoever. Though to @mliberty’s point, maybe the datasheet is actually just lacking in general vis-a-vis missing dynamic response.

It DOES make sense that, if you were going to throw in a nice beefy pull-down fet, you might use that internally to improve response under sudden load reduction, but it sure seems like the datasheet doesn’t offer any evidence of such. Which is weird mostly because it seems like a pretty big selling point, assuming the A variant is more expensive.

This absolutely happens with switch mode regulators. I usually see this happen powering radios (especially bursty ones with very high quiescent to active ratios), motors, and backlights. Anything that suddenly stops consuming power can cause this problem, especially if it is the only thing on it’s rail.

A dumb resistor to ground is a good way to diagnose it - add a few mA of quiescent and see if it goes away.

If it does, switching to a different control loop architecture is your best bet. Current mode and constant on time are good choices for bucks. Anything old school with an external network or a voltage mode control will be bad news.

Adding a giant capacitor often makes it worse because it just makes the loop less able to see what’s happening. Or it’ll make it look like it’s better and then a week later you’ll realize it’s way out of regulation.

Active discharge usually refers to a feature where the chip will discharge it’s rail to zero when it is disabled through a resistor and fet. This won’t help this problem. However, some chips that have this feature also use it in over voltage situations. You’ll need to check each datasheet to see whether it is just for disable or also for OV.

Regulators for dram are an overly expensive solution here too. They’re strongly bidirectional.

That’s exactly what I’ve always thought, and what the simplified schematic in the data sheet shows, which is why I’ve never paid much attention to the feature.

Indeed. Maybe there’s more to it than the simplified schematic shows, or maybe he’s just mistaken :slight_smile:

It can only happen if the switch mode has been designed incorrectly. Standard load regulation test is to run it at no load and instantaneous kick in very large load

Report back! Because this sounds pretty suspicous. I’m with @alexw, I’ve only ever seen “active discharge” as a load protection mechanism in regulators and load switches. There’s nothing to suggest that it’s part of the control loop in the datasheet…additionally the enable pin has a 0.4 - 1.2V threshold hysteresis further casting doubt on this as a usable mechanism.

It sounds like the tech perhaps misunderstood the issue.

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I came here just to say that too, I’ve been looking at the NCP718 very recently and my understanding was it only affects it when disabled, so the ramp down isn’t really slow presumably for a clean reset. I’m doubtful of the supports response that it affects the control loop. That just looks like poor dynamic response. I’ve found the NCP718 to be good in that respect though, better than a similar TI LDO which I had.

Coincidentally how did you get stock of the NCP718? At least for the 3V3 DFN Version I was looking at it was on crazy lead times and no stock.

Thanks for sharing this. I definitely am following this thread!

I am using the NCP176 series in a design which has two variants like the NCP718. I chose the NCP176B specifically because the design has multiple power supplies. The A version would not work as it would pull my other supply down when disabled.

The NCP176 datasheet mentions nothing about using the output discharge function for regulation. I find it strange that this detail would be left out as it would change the performance characteristics. At any case I will verify that I don’t have any issues.

The NCP176 does provide a load response. Some variants of the NCP176B are going EOL.

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