That helps, thank you @dlharmon! I’ll just have to mention that the iCE40 datasheet is not real clear on the setup and hold times for internal signals. I guess the user can somewhat trust the PNR tool to route things effectively to avoid violating setup/hold times for internal signals(?)
Separate but related question: is there a simple way to demonstrate metastability?
I’ve created a basic design that samples a pin, registers the value, and ouputs the same value to another pin. The D flip-flop is clocked on an internally-generated 1 kHz clock. I then generate a 200.5 Hz waveform (with obvious rise and fall times) that’s fed to the input pin. I trigger my scope on the input signal (blue). The output signal (yellow) shifts all around and changes its duty cycle. I’m guess that this is mostly just drift, but would metastability be visible on the output signal? Can you view it with an output pin, or does connecting a pin to the output of a flip-flop alleviate metastability issues?
