HDL for schematic capture


Has anyone had experience using HDL (VHDL or Verilog) for schematic capture? The more schematics I complete, the less value I see in the visual diagrams, especially when using packages that have over 1000 pins. I’ve spent the last 2 days wiring up a DDR4 DIMM to an FPGA, and I’m a little tired of dragging signals and wires around. Maybe I’m just ranting, but there has got to be a better way…

Well I better get back to the schematic…



There is a plugin for KiCad called SKiDL, which is exactly what you’re talking about! Check out Dave Vandenbout’s talk about it at KiCon this past year:


That looks like exactly what I need. Thanks for the info. Just like the video mentioned, I feel like I may have just hit rock bottom. I feel like my life in electronics is just connecting rectangles with lines and dots. Now there is hope!


That was fabulous, what a great speaker! Apart from mispronouncing KiCad, of course :sweat_smile:


Cadence had this pretty neat tool where you use a spreadsheet sheet to make a netlist and then it auto generated a semi readable schematic. It looked pretty useful for big digital designs. I’m sure some industrious python scripter could put together a similar workflow.


Cool. Thanks for the suggestions.