Sorry if this I’m missing the underlying requirement or limitations of the parts but are you free to swap Rx/Tx4 and Rx/Tx1 to make routing tidier (avoiding having to via onto a different signal layer for Rx/Tx1)? There’s also another pair of UART lines that could be swapped (on mobile so can’t type with the images enlarged).
I also wondered if you really want a copper pour on your signal layers. If they have a ground pour on the nearest inner layer, you are probably better off omitting them from what I understand of Rick Hartley et al.
I wish I could swap Rx/Tx4 and Rx/Tx1, however, in the STM32G070 bootloading application note it only mentions being able to boot from USART1, USART2, and USART3. Since I’m powering from Port 1, and the unit needs to be field reprogrammable the simplest solution for the end engineer was that they could plug their laptop into Port 1, with nothing else connected and upload the firmware. That meant either using vias or doing some funky routing; I opted for the vias. Even juggling the other ports I still ended up needing to ‘jump’ at some point.
As for the copper pours on the signal layer, I hold my hands up and admit I have no idea Time to hit YouTube I think.
Thanks for your comments - I really value you taking the time to respond.
I think Klaus means “on alternating layers”. The idea is to reduce PDN impedance and increase capacitance by adding stitched copper pours such that the pours produce Supply-GND “layer pairs”, albeit obviously pairs not covering the full board area. This also has the effect of bringing the supply closer (in the Z axis) to consuming devices, reducing CM noise thanks to shorter via length/inductance, especially as many popular stackups have the power plane buried deeply inside, meaning longer, more inductive, vias.
This approach has been championed by Rick Hartley, who’s shown some pretty dramatic improvement to a problematic 6-layer board. Rick tends to deal with very high-speed designs, so YMMV in less critical applications.
Regarding the SPI lines to the WIZ850, it looks like the spacing between the signals is about 2-3x the trace width but it looks like you can afford to go a little wider. Particularly in proximity to the clock signal, that should improve signal integrity.
BTW, do your connections have to be in that particular order? Ethernet on the left, usb master and then the isolated USB ports to the right?
Yes, thanks, Julia. English is not my first language
Alternate layers, with power signals plugged directly to planes with a via. Then the decoupling cap can be placed away from the IC if necessary. WIth planes, and a single 4.7uF cap, C201 and C203 is not needed (modern ceramic caps has low ESL even in big case sizes)
PDN impedance can be measured. But best is to mount a UFN connector and measure the quality of the VCC supply in the application to check that ripple is low
Yep, no reason not to increase the spacing of the SPI signals, so consider it done
Other than it seemed like a logical layout, the connector order could be altered, although they would all need to be at one side of the PCB. What did you have in mind?
So I have spent the day watching Mr Hartley and lots of memories of lectures 20+ years ago started coming back. I’m probably still as confused now as I was then
My current thinking is this: the isolated areas have top layer signal only to avoid chopping up the ground plane putting the traces on an inside layer. 2nd layer GND to minimise return paths, 3rd layer 5V and 4th layer GND again to minimise return paths on the power side.
For the Master Port the thinking is the same except the third layer would be 3.3V and the 4th layer would be GND and signal. I would then move the 5V section of the Master Port to an island, since it is contained in a relatively small area, with the same stack up.
The alternative would be to do 2 layer (it’s not a complex PCB after all), and route power and signals on the top layer, and a GND plane on the bottom. The downside I see here is that the distance between power and GND, and signal and GND are greater. Cost isn’t really a factor so I don’t see any intrinsic problem with using a 4 layer board.
From a signal integrity point of view I don’t think there would be any issues regardless of the stack up since all the signals are low speed. EMI of course is a different story.
This is obviously quite a bit of extra rework for potentially little gain and because I haven’t done the design nor have it in front of me to play with, it may not work out. However, I was wondering if you could rotate the stm32 180° and shorten the SPI lines, as well as perhaps only a couple of them needing to use bottom copper. Then have UART3 on the left of the ethernet connector as your master (and boot) USB. Then UART 2, 1, 4 in whatever pin order they come in to the left of the master USB connector. Would this free you from having to cross the UART lines over on bottom layer? I realise this doesn’t make things tidier in firmware, so perhaps not worth it as I’m sure your current design will be fine.
A new observation - did you make your UART traces as differential pairs? I’m not sure that’s needed and they may benefit from the greater spacing (moving the test points closer / elsewhere to accommodate), like the SPI lines.
That would indeed work, one of the other potential advantages would be that the crystal would be further away from the SPI lines. I think though I’m going to chance it on this one, and if all goes wrong you have provided plan B and and tell me I told you so
The serial lines are not routed in differential pairs (I don’t believe it is a requirement for UART pairs provided there isn’t a significant difference in length) and could certainly be opened up a bit. I’m not overly concerned with them since for this project there are only a handful of bytes being sent infrequently at 9600bps. Of course, I’m hoping we can reuse this somewhere else so I think I will increase the spacing since you never know what the next project might require.
Exactly what I would do. If you aren’t happy with it there will likely be things that neither of us have picked up, so getting a physical prototype in-hand is helpful, all other factors aside (like schedule / budget). You can incorporate more changes in that first revision.
No need for routing differential. If it was multi megabit, then maybe. Wavelength at 100MHz is 2m. Say 1/50th is outside waveguide theory, you need 40mm trace before it matters. At 9600 it is 4km if my math is right
Thanks Klaus, I’ve been thinking about this for a few days. If I calculate the wavelength of 100MHz of an electromagnetic wave through free space then I get 3m. However, if my understanding of how the wave propagates within a PCB is correct, we are not moving through free space, rather the dielectric medium. Therefore, would I be right in saying the speed is going to be different, and in turn, changes the wavelength?
Also, is the 1/50th based on the harmonic frequencies of the wave being negligible at that point?
Speed of light is different in materials. FR4 is actually half, so 150*10^6m/s
So for 100MHz, the wavelength is 1.5m
The dipole emits different power wrt the length. So lower than the wavelength the power is reduced by the square of the reduction in length
So imagine you have a cable connected to your box that is 1.5m long. It will emit lots of radiation
A PCB trace on the PCB with 3cm (1/50th) has 2500 times lower radiation
When you get close to the wavelength (L is larger then 1/5), then it begins to radiate proportional to the length (not squared)
My PCB arrived on Thursday. I had ordered the board (almost) fully assembled, so after adding the FT232 IC’s, the programming header and the Wiz850io module the fun began.
I started by plugging in the master usb port. The 5V and 3V lets turned on. At least there wasn’t a catastrophic problem. The LEDs on the boot mode and debug mode switches worked as expected. Connecting the ST-Link, I was able to communicate with the MCU. LED’s were then all checked along with the reset switch.
Clock frequency was then tested with my frequency counter and was measured at 15.9999347MHz giving a 0.00000408% deviation. My guess is that the deviation comes from the stray capacitance being slightly different from the guessed value. I would need to verify against the other boards to see if it would be worth tweaking the load capacitor values on future boards.
Next I programmed the FT232 IC’s which didn’t provide any unwanted excitement. These were then tested at 115200bps and exhibited no data integrity issues. Enabling the WizNet 850io also didn’t provide any issues (SPI bus @ 16Mbit). Last to test was the last minute addition of an M24C64 EEPROM. Again this worked as expected.
So all in all, the PCB behaves as designed. If I was revising it I would choose a different EEPROM - something like a 24AA02E64 which would have had the addition benefit of providing a unique MAC address for the 850io.
Time to hit YouTube I think.
