Christian Tenllado's build log

I builded that board, which was my first board, two years ago, and it blinked :slight_smile:

First try? If so, you did better than me :smiley:

Last weeks I was thinking on joining the program and decided to try to make a slight modification of the Shine on you crazy kicad board, that would include two push buttons and connect the two leds to two GPIO pins. The final board was send to OSH park two weeks ago. I am waiting for the parts and board to arrive and see if it works.

Yes that Getting to blinky was my first board, first try. I had to modify the battery holder because I was ordering from mouser for some reason I do not remember, and it was great experience.

I want to upload the pictures of my version of the shine on you… board, but I am not allowed. As I deleted my old account, now I am new and I can only upload one image, a will have to wait.

Well, this week I have been busy with the CE Header, and I start to have some doubts and questions that I would like to share with you. I am afraid that it is a bit difficult to describe without images so I will wait until I am allowed to upload the pictures.

Ok, here go the figures for the layout and the 3D view of my shine on board:

Well the pin header should be female, but that is the 3D model that came with the footprint. I have seen in the build log of @Steve_Mayze that you can modify them with wings3D, but I am still not there :slight_smile:

And finally, my questions for you guys about the CE Header routing. I have been tinkering with it, and will probably do it a little bit more after seeing some of the layouts of others. But I would like to be able to learn which layout is better and why, because there are many possibilities.

So here goes one specific question. Routing the analog pins, I have for instance these two options:

a) analog traces on the FCu layer, but AIO_3 passes close to the I2C_SCLK and I2C_SDAT pins. Ground layer is shielding most of the traces.

b) AIO_3 routed on the BCu layer, going bellow of other two analog traces. GND plane covers these traces a little bit less.

Is any of these better than the other?

And for the right side of the board, I am not very satisfied with all those vias. I like the routing showed by @Steve_Mayze in his build log (Steve's Build Log), which seems cleaner than mine. My question is, apart from aesthetics, would there be any practical differences between both routings?

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Even though it might pass closer to the other traces on board, I’d recommend keeping the trace on top if possible. Having a more solid ground plane is more worthwhile in my opinion. If you were doing a 4 layer board, the math would change because the ground plane would be solid (on an inner layer).

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Thanks for your reply Chris, this is the kind of knowledge that comes from experience that is harder to find for me. As a rule of thumb then, keeping the traces shielded with the ground plane is better, great.

Finally I had some time today to redo the routing of some parts, here is my final layout for the CE Header, trying to have the largest coverage from the ground plane.

Borrowing the ideas from Steve's Build Log I also created a 3d model for the header pins (get it from here if you want it, the 3d view of the board, with labels on each pin is:

I have been working on the Sensor Board for the CE Header. I rotated the shift register to simplify the routing and used two ground planes, one for the analog part and one for the rest. I connected both at one end. The resulting layout and the corresponding 3D view images are:

I am still uncertain of the capacitor that @ChrisGammell connected to the latch pin. I do not understand why that capacitor is there. I posted a question in the Sensor Board Schematic topic (Sensor Board Schematic), to see if somebody can help me to understand the function of that capacitor. For the moment I did not include that capacitor in my design. I might include it in the future if I think it might be needed.

As responded in that thread, you don’t need to populate it, but you might want to leave the footprint in there.

I just updated the pcb with the capacitor in the latch pin.

Is there a cutout on the ground plane above R8/D8? Any reason for that?

Well, yes, I used a small ground plane for the photoresitor, as the plan was using ADCs to read the voltage, just to isolate it a little bit from the digital temperature sensor above (U2). Both planes are joined at one place, just to the left of the R8 label. I thought this was convenient, but of course I am not sure. I would appreciate if you can tell me if this was just over thinking the layout and it does not make much sense or whatever you see about it. It would help me to learn from the experience.

I was a bit busy last weeks and I could not spend much time on CE. All I did is building my modified version of the shine on you crazy kicad board. I builded the three boards and tested that they actually work. My soldering was not very good, but I am happy to see the boards working.

I uploaded a video to youtube showing the test on the board. A simple bash script using the gpio command makes the two leds blink and the blinking stops if I push one of the buttons. This way I tested that I can read a digital pin from the buttons and write to the digital pins connected to the leds.

Great experience.

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