Correct, the discharge low voltage for a sink current of 15 ma and Vdd of 5V is typically 0.2V but if you look at the graph a sink current of 15 ma for a Vdd of 2V gives a much higher low voltage of 1V. To get it back to the 0.2V range we need to reduce the sink current to 8 ma or less. As you stated 470R would give around 6 ma. As you can see by the graph too much sink current increases the discharge low voltage which starts to affect your timing. You could probably increase Ra further to 1K or more but it will decrease the symmetry of your waveform. But even at 1K it changes the symmetry by less than a 1% in your case.
For silicon transistors the VBE(sat) or the base to emitter saturation voltage is around +/-0.6 to 0.7 volts. This varies with current and temperature but for most circuits, especially logic circuits, we can assume a value of +/-0.7 V. That means for a NPN transistor the base voltage needs to be 0.7V more positive than the emitter voltage for the transistor to turn on. For PNP transistors the base voltage needs to be 0.7 V more negative than the emitter voltage. Transistors are not a perfect switch, how much they turn on varies with base voltage/current, collector current, DC gain, temperature, .... this is why there are usually so many graphs on a transistor datasheet.
Using your simulator you could simulate a circuit consisting only of the transistors as you've drawn them above and vary the voltage on the base from 0 to 3 V and see when each transistor turns on and off.
Correct me if I'm wrong, but as some of you seem to be doing these projects as part of a course I assume they are meant to be a learning experience so I am trying not to just give you all the answers but rather steer you down the path where you can discover them on your own. If I'm helping too much or not enough just let me know.